1. Field of the Invention
The invention relates to a digital phase shift phase-locked loop for data and clock recovery.
2. Description of the Related Art
The phase-locked loop device is frequently used for the high-speed Ethernet application having a transmission rate up to 100 Mbps. A timing clock is generated by the voltage-controlled oscillator (VCO) of the phase-locked loop and is made synchronous with the received signal by a phase detector and a loop filter such that data recovery can be accomplished. FIG. 8 shows a conventional phase-locked loop which comprises a phase detector 71, a loop filter 72, and a voltage-controlled oscillator 73. The conventional phase-locked loop has the following disadvantages:
1. The input voltage of the voltage-controlled oscillator is continuously adjusted during the process of synchronizing the timing clock with the received data, which alters the frequency and phase of the output clock simultaneously. When the jitter of the received data results from transmission line decay is very severe, it may cause serious frequency drift which leads to erroneous result of data recovery, or what is worse, make the whole phase-locked loop out of locked range and synchronization thus becomes impossible. PA1 2. The loop filter of a phase-locked loop is mainly composed of resistors and capacitors, while each of a resistor and a capacitor occupies a substantial area of the chip with the present integrated-circuiut fabrication technology.
Therefore, the primary object of the invention is to provide a phase shift phase-locked loop which synchronizes the output clock with the received data by adjusting the phase of the output clock without changing its frequency.
Another object of the invention is to provide a phase shift phase-locked loop whose corresponding integrated-circuit occupying a much smaller area than what prior phase-locked loops occupy.